Echelon FTXL Hardware - Manual (Page 8)

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FPGA Design for the FTXL Transceiver......................................................... 37
Overview ....................................................................................................... 38
Using the Reference Design ........................................................................ 38
Developing a New FPGA Design................................................................. 38
FPGA Device Requirements ................................................................. 39
Nios II Processor.................................................................................... 40
FPGA Configuration Device.................................................................. 40
FTXL Components................................................................................. 41
FTXL Parallel Interface Delay....................................................... 42
FTXL Parallel I/O Transceiver Interface ...................................... 43
FTXL Service LED.......................................................................... 46
FTXL Service Pin ............................................................................ 47
FTXL Transceiver Interrupt .......................................................... 47
FTXL Transceiver Reset................................................................. 47
Phase-Locked Loop ................................................................................ 48
DBC2C20 Components.......................................................................... 48
Timers .................................................................................................... 48
External Memory................................................................................... 48
Addressing, Size, and IRQ Requirements............................................ 49
FTXL Hardware Abstraction Layer............................................................ 50
Other Hardware Design Considerations .................................................... 51
Working with the Altera Development Environments ................................... 53
Development Tools....................................................................................... 54
Using a Device Programmer for the FPGA Device .................................... 55
Setting Component Search Paths ............................................................... 56
Adding FTXL Components to an Existing Design..................................... 57
Modifying the SOPC Builder Design.................................................... 57
Modifying the Quartus II Design ......................................................... 60
Building the Application Image .................................................................. 61
Loading the Application Image into the FPGA Device.............................. 62
Using the Bring-Up Application to Verify FTXL Hardware Design .............. 63
Overview ....................................................................................................... 64
Application Framework......................................................................... 64
Interrupt Functions from the FTXL HAL............................................ 64
FTXL Transceiver Interface ........................................................................ 65
Reset Signal ........................................................................................... 65
Status Signals........................................................................................ 66
Data Register ......................................................................................... 66
Interrupt................................................................................................. 68
Working with the Nios IDE for the Bring-Up Application........................ 69
Creating a New Application Project..................................................... 69
Building the Application Image............................................................ 70
Running the Application from the Nios IDE ....................................... 70
Running the Tests........................................................................................ 70
Reset Test...............................................................................................71
Token Passing Test................................................................................ 73
Data Passing Test.................................................................................. 76
Interrupt Test ........................................................................................ 78
Service Pin and LED Test..................................................................... 79
Designing Additional Tests ......................................................................... 80
Index................................................................................................................. 81