Echelon FTXL Hardware - Manual (Page 32)

24 FTXL Transceiver Hardware Interface
The FTXL LonTalk protocol stack and the FTXL Transceiver pass the write
token alternatively between themselves on the bus in an infinite ping-pong
fashion. The owner of the token has the option to write a series of data bytes, or
alternatively, pass the write token without any data.
The owner of the token can transfer up to 255 bytes of data. The FTXL LonTalk
protocol stack reads the HS bit of the status register prior to reading or writing
each data byte. The token owner keeps possession of the token until all data
bytes have been written, after which it passes the token to the attached device.
The other device can then repeat the same process or it can pass the token back
without any data.
The FTXL LonTalk protocol stack reads or writes data by first asserting the CS~
signal, then deasserting it. For a host read operation, the assertion causes the
FTXL Transceiver to put data on the bus so that the FTXL LonTalk protocol
stack can read it. For a host write operation, the assertion causes the FTXL
Transceiver to read data on the bus and store it in its input buffer. In both cases,
the data is latched on the rising edge of the CS~ signal.
FTXL Transceiver Pin Characteristics
The FTXL Transceiver includes the following sets of pins:
• Eight I/O pins
• An interrupt request (IRQ) pin
• A reset pin
• A service pin
• Clock pins
• L
ON W ORKS network I/O pins
The following sections describe the characteristics of the I/O, IRQ, Reset~,
Service~, and clock pins. See the
FT 3120 / FT 3150 Smart Transceiver Data
Book for information about other pins, including the requirements for the V
DD
and ground pins.
I/O Pins
The I/O pins (IO0-IO10) have a standard sink capability (1.4 mA @ 0.4 V), and
have TTL level inputs with hysteresis.
Because the CS~ line (IO8) is asynchronous, it should be kept as noise-free as
possible. For example, you should add a 100 pF debounce capacitor to this line.
Important: To ensure that noise-levels for all communications lines between the
FPGA device and the FTXL Transceiver are kept to a minimum, you should
ensure that the FPGA device and FTXL Transceiver are separated by no more
than 10 cm on the FTXL device’s PCB.
IRQ Pin
The IRQ pin (pin 24) is an output pin. For an FT 3120 Smart Transceiver, this
pin is the CP3 Sleep~ pin. However, for an FTXL 3190 Free Topology Smart