Overview, Using the reference design, Developing a new fpga design – Echelon FTXL Hardware User Manual
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FPGA Design for the FTXL Transceiver
Overview
The hardware for an FTXL device consists primarily of an FTXL Transceiver
Chip and an Altera FPGA device. When designing your FTXL device, you can
use the reference design that is included with the FTXL Developer’s Kit or you
can create your own FPGA design and include the required FTXL components.
Using the Reference Design
The FTXL Developer’s Kit provides a reference design for the FPGA hardware
design. You can use this design as is for an FTXL device that uses the same
underlying hardware as the DBC2C20 development board, or you can modify the
design for a different development board or production device.
The reference design is located in the
[
NiosEDS
]\examples\vhdl\DBC2C20_FTXL\Standard directory, where
[
NiosEDS
] is the directory to which you installed the Nios II Embedded Design
Suite (EDS), usually C:\altera\72\nios2eds. You should create a backup copy of
this design before modifying it.
To work with the reference design, you must use the Altera Quartus II software,
version 7.2 or later (either the Web Edition or the Subscription Edition). Within
the Quartus II software, you must:
• Set up the USB Blaster download cable so that you can load the design
into the FPGA device on the DBC2C20 development board; see
Device Programmer for the FPGA Device
on page 55.
• Add the FTXL and DBC2C20 components to the global or project search
path; see
Setting Component Search Paths
on page 56.
• If you modify the reference design, recompile the project; see
on page 61.
• Load the design into the FPGA device on the DBC2C20 development
board; see
Loading the Application Image into the FPGA Device
on page
Developing a New FPGA Design
During development of a new FPGA design for an FTXL Transceiver, your design
needs to address the following considerations:
• Which type of physical FPGA device to use
• Which type of Nios II processor to use
• Which FPGA configuration device to use
• How to design for the FTXL parallel interface
• How to modify the FTXL hardware abstraction layer (HAL) for the
software project
This chapter addresses these considerations for an FTXL device.