Echelon FTXL Hardware - Manual (Page 48)

40 FPGA Design for the FTXL Transceiver
multipliers, embedded memory blocks, phase-locked loops (PLLs), and high-speed
differential I/O channels.
See the Altera Cyclone II Device Handbook or Cyclone III Device Handbook for
more information about these FPGA devices.
Although the FTXL Transceiver has not been tested with an Altera Stratix
® ,
Stratix GX, or Arria™ GX FPGA device, there is no restriction within the FTXL
hardware or software design that prevents your FTXL device from using one of
these types of FPGA device. Likewise, there is no restriction on porting your
FTXL device to an Altera Hardcopy ® II or Hardcopy Stratix structured ASIC
device.
Nios II Processor
The FTXL Developer’s Kit reference design uses a Nios II/s processor with the
following characteristics:
• Embedded multipliers
• No hardware divide
• Reset vector set to the cfi_flash at offset 0x0
• Exception vector set to the sdram at offset 0x20
• 4 KB cache for the instruction master
• Bursts disabled for the instruction master
• No tightly coupled instruction master ports
• Default settings for the data master
• No advanced features selected
• JTAG Level 1
• No custom instructions
Your FTXL device design can use either a Nios II/s or Nios II/f processor with
similar settings as those of the FTXL Developer’s Kit. However, the Nios II/e
processor might not have sufficient resources for an FTXL device.
See the Altera
Nios II Processor Reference Handbook for more information about
the Nios II processor.
FPGA Configuration Device
The FTXL Developer’s Kit reference design hardware uses an EPCS16 serial
configuration device. Your FTXL device design can use any configuration device
that is appropriate for your design’s FPGA device.
In the Quartus II Device and Pin Options dialog, the configuration device uses
the active serial configuration and generates compressed bit streams, as shown in
Figure 17 on page 41. The configuration device uses default settings.