Echelon Neuron - Manual (Page 78)

AND (And)
The AND instruction performs a logical AND for two numbers. The AND
instruction uses one of two addressing modes:
• In implicit addressing mode, the AND instruction retrieves both TOS and
NEXT from the data stack and performs a bitwise logical AND for them.
TOS and NEXT are consumed, and the result is placed in TOS. The
operation clears the Carry flag.
• In immediate addressing mode, the AND instruction (AND #number)
performs a bitwise logical AND for a specified constant number with the
value of TOS, and the result is placed in TOS. The value of number must
resolve at link time to a value in the range -128 to +127. The operation
clears the Carry flag.
The AND instruction applies to Series 3100, 5000, and 6000 devices.
Syntax:
In implicit addressing mode, the AND instruction requires no operands:
AND
In immediate addressing mode, the AND instruction requires one operand:
AND #number
The number sign or hash (#) is required to specify the immediate value.
Table 14 describes the attributes of the AND instruction.
Table 14. AND Instruction
Instruction Hexadecimal
Opcode
Instruction
Size (Bytes)
CPU Cycles
Required
Affect on
Carry Flag
AND 51 1 4 Cleared
AND #number 59 2 3 Cleared
Example:
The following example performs the operation 2 AND 3 AND 4.
pushs #2 ; (2, -, -)
pushs #3 ; (3, 2, -)
and ; (2, -, -)
and #4 ; (0, -, -)
The value of TOS after the first AND instruction is 2 because 2 AND 3 = 2. The
AND #4 instruction performs a logical AND of 4 with TOS (4 AND 2), so that
TOS then contains 0.
68 Neuron Assembly Language Instruction Statements