Echelon Neuron - Manual (Page 27)

A Neuron Chip or Smart Transceiver is a big-endian device, that is, the most-
significant byte (MSB) of an address or a 16-bit scalar is at a lower memory
address, and the least-significant byte (LSB) of an address or a 16-bit scalar is at
a higher memory address. For 16-bit addresses, a Neuron assembly language
function must be sure to read or write the MSB at a low address before reading or
writing the LSB at higher address.
Because the data stack grows towards higher addresses, 16-bit entities appear on
the data stack with the LSB nearer to TOS. For the return stack, which grows in
the opposite direction, 16-bit entities appear with the MSB nearer to TOS.
Most operations that require arguments require that these arguments are
pushed onto a stack, and when an operation is performed, its arguments are
popped from a stack and its result (if any) pushed back on.
In addition to the DSP, a Neuron assembly language function can use two
registers, TOS and NEXT, to work with the top of the stack and with the next
element below the top of the stack, respectively. See Overview of Stack-Oriented
Programming for additional information about working with stacks.
For more information about the Neuron architecture:
• For Series 3100 devices, see the FT 3120 / FT 3150 Smart Transceiver
Data Book or the PL 3120 / PL 3150 / PL 3170 Power Line Smart
Transceiver Data Book.
• For Series 5000 devices, see the Series 5000 Chip Data Book.
• For Series 6000 devices, see the Series 6000 Chip Data Book.
Hardware Resources for Assembly Programs
The Neuron architecture provides two major sets of hardware resources for a
Neuron assembly language function to use: CPU registers and stacks. To make
effective use of these resources, the Neuron assembly language implements a
number of addressing modes that provide efficient access to data, either through
the registers or through one of the stacks. The following sections describe these
hardware resources. See Addressing Modes for a description of the available
addressing modes.
CPU Registers
The Neuron architecture provides the following types of CPU registers for
Neuron assembly language programming:
• General-purpose 16-bit pointer registers and 8-bit data registers
• A flag register
• An instruction pointer
• A base-page register
• A data-stack pointer register (8-bit, BP-relative)
• A register containing the element on top of the data stack (TOS)
• A return-stack pointer register (8-bit, BP-relative)
The following sections describe these registers.
Neuron Assembly Language Reference 17