General-purpose registers – Echelon Neuron User Manual

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General-Purpose Registers

The Neuron architecture defines 16 hardware memory locations that the Neuron

Assembler uses as general-purpose registers, typically named R0, R1, R2, and so

on, to R15, as described in Table 6. Each of the general-purpose registers is

eight bits wide.

Table 6. General-Purpose Registers

General-

Purpose

Register

Description

Scratch register. A function can use this register as needed.

Assume that any call to the firmware, or to any function in a

library or written in Neuron C, might change the contents of

this register.

Scratch register. A function can use this register as needed.

Assume that any call to the firmware, or to any function in a

library or written in Neuron C, might change the contents of

this register.

Scratch register. A function can use this register as needed.

Assume that any call to the firmware, or to any function in a

library or written in Neuron C, might change the contents of

this register.