Indirect indexed, Dsp relative – Echelon Neuron User Manual

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Example:

push [P0][12] ; ( )

pop [P3][4] ; ([P3][4], ...)

The push [P0][12] instruction pushes the 12th byte from the address contained

in the P0 general-purpose pointer register onto the data stack by adding the

value of the second operand (12) to the value of the P0 pointer register. The pop

[P3][4] instruction pops the value in TOS to the location specified as 4 bytes from

the value of the P3 pointer register.

Indirect Indexed

In the indirect-indexed addressing mode, the instruction takes two operands: a

pointer register (P0, P1, P2, or P3) or an expression that resolves to a pointer

mode, the offset can be any value. In contrast with the direct addressing modes,

which uses constant offset values, this addressing mode uses variable offset

values in the 0..255 range, contained in TOS.
Example:

pop [P0][tos] ; ( )

push [P3][tos] ; ([P3][4], ...)

The pop [P0][tos] instruction pops the value of NEXT from the stack and places

it into the location specified by adding the value of TOS to the value of the P0

pointer register. The push [P3][tos] instruction pushes the value from the

location specified by adding TOS to the value of the P3 pointer register into

NEXT on the stack.

DSP Relative

In the DSP-relative addressing mode, the instruction takes two operands: the

data stack pointer (DSP) and a negative displacement value or expression that

resolves to a negative displacement value. The displacement must be in the

range -1 to -8.
Example:

; (t, n, a, b, c, d, e --)

push [dsp][-1] ; (a, t, n, a, b, c, d, e -- )

pop [dsp][-4] ; (t, n, a, b, c, a, e --)

The push [dsp][-1] instruction pushes the a copy of the first element below

NEXT into TOS (‘a’ in this example). The pop [dsp][-4] instruction pops the

value held in TOS into the fourth stack element below NEXT.
The DSP-relative offset refers to the position before the instruction executes.
See Documenting Changes to the Stack for information about the importance of

using stack comments like those in the example to document how the

instructions affect the stacks.

Neuron Architecture for Neuron Assembly Programming