Pointer registers – Echelon Neuron User Manual

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A scratch register is one that can be used for temporary data storage by multiple

programs or functions. Although some operations support a special addressing

mode to index data through the general-purpose registers, you should consider

registers R0..R2 as modified after calling any other function. See Chapter 8,

System-Provided Functions, for a description of these functions, including which

general-purpose registers each function uses and modifies.
Important: Do not use or modify R4 in your Neuron assembly functions because

the network processor uses it. Modifying the other reserved general-purpose

registers (R3 to R15) can also cause unpredictable results.
The Neuron Assembly language refers to the general purpose data registers by

their base-page relative indices, 8..23. A typical assembly language function

defines the mnemonics R0 to R15 for these registers by using the EQU assembly

directive.
Example: The following push instruction uses base page relative addressing.

This addressing mode addresses the argument through one operand, the index of

one of the general purpose data registers within the base page. This index must

be in the 8..23 range.
The following instruction pushes the value of the R0 register onto the data stack:

push !8

Defining mnemonic names for the general-purpose registers makes this

instruction more easily readable. The following example is equivalent to the

previous one:

R0 EQU 8

push !R0

However, because you define the R0 mnemonic, it carries no special meaning for

the Neuron Assembler. The Assembler does not validate that the mnemonic

refers to the correct or intended register.
For the purpose of clarity (and unless explicitly mentioned to the contrary), all

source code examples in this book assume that the following mnemonics are

defined:

R0 EQU 8

R1 EQU R0+1

...

R15 EQU R14+1

Finally, note that the mnemonics are user-defined symbols. Unlike pre-defined

Pointer Registers

The Neuron architecture defines four general-purpose pointer registers, typically

named P0, P1, P2, and P3, as described in Table 7. Each of the pointer registers

is 16 bits wide.

Neuron Assembly Language Reference