Echelon Neuron - Manual (Page 103)

OR (Or)
The OR instruction performs a logical OR for two numbers. The OR instruction
uses one of two addressing modes:
• In implicit addressing mode, the OR instruction retrieves both TOS and
NEXT from the data stack and performs a bitwise logical OR for them.
TOS and NEXT are consumed, and the result is placed in TOS. The
operation clears the Carry flag.
• In immediate addressing mode, the OR instruction performs a bitwise
logical OR for a specified one-byte constant number with the value of
TOS, and the result is placed in TOS. The value of number must resolve
at link time to a value in the range -128 to +127. The operation clears the
Carry flag.
The OR instruction applies to Series 3100, 5000, and 6000 devices.
Syntax:
In implicit addressing mode, the OR instruction requires no operands:
OR
In immediate addressing mode, the OR instruction requires one operand:
OR #number
The number sign or hash (#) is required to specify the immediate value.
Table 36 describes the attributes of the OR instruction.
Table 36. OR Instruction
Instruction Hexadecimal
Opcode
Instruction
Size (Bytes)
CPU Cycles
Required
Affect on
Carry Flag
OR 52 1 4 Cleared
OR #number 5A 2 3 Cleared
Example:
The following example performs the operation 2 OR 3 OR 4.
pushs #2 ; (2, -, -)
pushs #3 ; (3, 2, -)
or ; (3, -, -)
or #4 ; (7, -, -)
The value of TOS after the first OR instruction is 3 because 2 OR 3 = 3. The OR
#4 instruction performs a logical OR of 4 with TOS (4 OR 3), so that TOS then
contains 7.
Neuron Assembly Language Reference 93