Flag register, Instruction pointer, Base-page register and stack registers – Echelon Neuron User Manual

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P0 EQU 0

P1 EQU 1

P2 EQU 2

P3 EQU 3

Finally, note that the mnemonics are user-defined symbols. Unlike pre-defined

Flag Register

The flag register (FLAGS) is an 8-bit data register that contains the Carry flag

and other flags that are used by the system firmware. The Carry flag is the

most-significant bit of register, as shown in Figure 1.
A Neuron assembly function would rarely use the FLAGS register explicitly;

however, a number of assembly instructions for conditional branches and

arithmetic use the Carry flag from this register.

reserved

carry flag

Figure 1. Flag Register Bits

Instruction Pointer

The instruction pointer (IP) is a 16-bit address register that contains the address

of the next instruction to be executed. It is explicitly modified by call, branch,

and return instructions. Conditional branch instructions (when the branch is not

taken) and all other Neuron assembly instructions implicitly increment the IP by

the size of the instruction.

Base-Page Register and Stack Registers

Each of the Neuron processors has its own base page area in the data space. The

base pages are established at device startup by an initialization function. Any

remaining data space that is not used for base pages can be used as global

variable space.
A base page area has four parts:

•

General-purpose pointer registers

•

General-purpose data registers

•

Data stack and data-stack register

•

Return stack and return-stack register

Figure 2 shows an example for the layout of a base page, including all of the

registers that are available for Neuron assembly language programming.

Neuron Assembly Language Reference