Echelon Neuron - Manual (Page 26)

Neuron Architecture
For Series 3100 devices, the architecture of a Neuron Chip or Smart Transceiver
includes three independent processors that share a common memory, arithmetic-
logic unit (ALU), and control circuitry. Each processor has its own set of
registers, including an instruction pointer (IP) and a flag register (FLAGS),
which contains the processor ID and the Carry flag.
For Series 5000 and 6000 devices, the architecture of a Neuron Chip or Smart
Transceiver is essentially identical to the independent processors of a Series 3100
device; however, Series 5000 and 6000 devices also provide interrupt-processing
support. Depending on the device’s configuration, interrupts can run in a fourth
processor or share the main application processor. As with Series 3100 devices,
each processor has its own set of registers, including an instruction pointer (IP)
and a flag register (FLAGS), which contains the processor ID and the Carry flag.
The Neuron architecture uses a base page model for addressing memory. Each
processor has a base-page register (BP) that points to a 16-byte boundary in
RAM. The first eight bytes of the base page are used as four 16-bit pointers
(named P0 to P3), followed by 16 bytes that implement 16 one-byte data registers
(named R0 to R15).
Some addressing modes refer to those general-purpose registers, and one
addressing mode directly accesses all 256 base-page bytes, including the 24 bytes
for the general-purpose registers.
Many of the general-purpose registers have a pre-defined use within the Neuron
system firmware and application framework. See CPU Registers for more
information.
Base-page pointers or the direct addressing mode is used to access to global data
(defined as memory outside the base page).
Neuron Chips and Smart Transceivers are stack-oriented machines, using two
stacks: the data stack and the return stack. The data stack holds program data,
and the return stack holds return addresses and transient local data. In the
event of an interrupt, the return stack also holds some of the processor’s state
information.
The data stack’s starting address is at low base page memory (after the general-
purpose register area), and moves upward. The data stack pointer (DSP) is an 8-
bit offset from the BP register. The return stack’s starting address is at the top
of the base-page memory, and moves downward. The return stack pointer (RSP)
is an 8-bit offset from the BP register.
A dedicated hardware register holds the top of data stack element (this element
is called TOS), and a special addressing mode allows for fast access to the
element below TOS (this element is called NEXT).
This stack-oriented architecture, with both data and return stacks growing
towards each other within the same 256-byte base page, is not normally
problematic, but deep recursion or large local variables, or a combination of both,
should be avoided to prevent the stacks from colliding. The programmer is
responsible for seeing that the two stacks never collide. For Series 5000 and
6000 devices, a stack collision or a stack underflow can be recognized by the
system firmware, and results in an entry in the device’s error log.
16 Neuron Architecture for Neuron Assembly Programming