Echelon Neuron - Manual (Page 75)

ADD (Add)
The ADD instruction adds two numbers. The ADD instruction uses one of two
addressing modes:
• In implicit addressing mode, the ADD instruction retrieves both TOS and
NEXT from the data stack and adds them together. TOS and NEXT are
consumed, and the result is placed in TOS. The operation modifies the
Carry flag as result of the unsigned addition.
• In immediate addressing mode, the ADD instruction (ADD #number)
adds a specified one-byte constant number to the value of TOS, and the
result is placed in TOS. The value of number must resolve at link time to
a value in the range -128 to +127. The operation modifies the Carry flag
as result of the unsigned addition.
The ADD instruction applies to Series 3100, 5000, and 6000 devices.
Syntax:
In implicit addressing mode, the ADD instruction requires no operands:
ADD
In immediate addressing mode, the ADD instruction instruction requires one
operand:
ADD #number
The number sign or hash (#) is required to specify the immediate value.
Table 11 describes the attributes of the ADD instruction.
Table 11. ADD Instruction
Instruction Hexadecimal
Opcode
Instruction
Size (Bytes)
CPU Cycles
Required
Affect on
Carry Flag
ADD 50 1 4 Modified
ADD #number 58 2 3 Modified
Example:
The following example performs the operation 2+3+4.
pushs #2 ; (2, -, -)
pushs #3 ; (3, 2, -)
add ; (5, -, -)
add #4 ; (9, -, -)
The value of TOS after the first ADD instruction is 5 because 2+3 = 5. The ADD
#4 instruction adds 4 to TOS (4+5), so that TOS then contains 9. The value of the
Carry flag is modified (cleared) after each of the add instructions because neither
unsigned addition requires an extra carry bit.
Neuron Assembly Language Reference 65