Echelon Neuron - Manual (Page 115)

Instruction Hexadecimal
Opcode
Instruction
Size (Bytes)
CPU Cycles
Required
Affect on
Carry Flag
PUSH address B7 3 7 None
PUSH TOS A4 1 3 None
PUSH NEXT A5 1 4 None
PUSH #number B4 2 4 None
PUSH !8 88 1 4 None
PUSH !9 89 1 4 None
PUSH !10 8A 1 4 None
PUSH !11 8B 1 4 None
PUSH !12 8C 1 4 None
PUSH !13 8D 1 4 None
PUSH !14 8E 1 4 None
PUSH !15 8F 1 4 None
PUSH !16 90 1 4 None
PUSH !17 91 1 4 None
PUSH !18 92 1 4 None
PUSH !19 93 1 4 None
PUSH !20 94 1 4 None
PUSH !21 95 1 4 None
PUSH !22 96 1 4 None
PUSH !23 97 1 4 None
PUSH [RSP] A1 1 4 None
PUSH !TOS A6 1 4 None
Neuron Assembly Language Reference 105