Cirrus Logic CS61884 - Manual (Page 42)

CS61884
42 DS485F3
14.33 Status Registers
The following Status registers are read-only: LOS
Status Register (04h) (See Section 14.5 on
page 35), DFM Status Register (05h) (See Sec-
tion 14.6 on page 35) and AIS Status Register
(13h) (See Section 14.20 on page 39). The
CS61884 generates an interrupt on the INT pin any
time an unmasked status register bit changes.
14.33.1 Interrupt Enable Registers
The Interrupt Enable registers: LOS Interrupt En-
able Register (06h) (See Section 14.7 on page 36),
DFM Interrupt Enable Register (07h) (See Sec-
tion 14.8 on page 36), AIS Interrupt Enable Reg-
ister (14h) (See Section 14.21 on page 39) and
AWG Overflow Interrupt Enable Register
(1Ah)
(See Section 14.27 on page 41) , enable
changes in status register state to cause an interrupt
on the INT pin. Interrupts are maskable on a per
channel basis. When an Interrupt Enable register
bit is 0, the corresponding Status register bit is dis-
abled from causing an interrupt on the INT pin.
NOTE: Disabling an interrupt has no effect on the sta-
tus reflected in the associated status register.
14.33.2 Interrupt Status Registers
The following interrupt status registers: LOS In-
terrupt Status Register (08h) (See Section 14.9
on page 36), DFM Interrupt Status Register
(09h) (See Section 14.10 on page 36), AIS Inter-
rupt Status Register (15h) (See Section 14.22 on
page 40) and AWG Overflow Interrupt Status
Register (1Bh) (See Section 14.28 on page 41), in-
dicate a change in status of the corresponding status
registers in host mode. Reading these registers
clears the interrupt, which deactivates the INT pin.