AMD SimNow Simulator 4.4.4 - Manual (Page 224)

AMD Confidential
User Manual September 12
h
, 2008
212 Appendix A
Instruction
Supported
Mnemonic Opcode Description
ROR reg/imm32,1 D1 /0
Rotate a 32-bit register or memory
operand left 1 bit.
ROR reg/mem32,CL D3 /0
Rotate a 32-bit register or memory
operand right the number of bits
specified in the CL register.
ROR reg/mem32,imm8 C1 /0 ib
Rotate a 32-bit register or memory
operand right the number of bits
specified by an 8-bit immediate
value.
ROR reg/imm64,1 D1 /0
Rotate a 64-bit register or memory
operand right 1 bit.
ROR reg/mem64,CL D3 /0
Rotate a 64-bit register or memory
operand right the number of bits
specified in the CL register.
ROR reg/mem64,imm8 C1 /0 ib
Rotate a 64-bit register or memory
operand right the number of bits
specified by an 8-bit immediate
value.
SAHF 9E
Loads the sign flag, the zero flag,
the auxiliary flag, the parity flag,
and the carry flag from the AH
register into the lower 8 bits of the
EFLAGS register.
SAL reg/mem8,1 D0 /4
Shift an 8-bit register or memory
location left 1 bit.
SAL reg/mem8,CL D2 /4
Shift an 8-bit register or memory
location left the number of bits
specified in the CL register.
SAL reg/mem8,imm8 C0 /4 ib
Shift an 8-bit register or memory
location left the number of bits
specified by an 8-bit immediate
value.
SAL reg/mem16,1 D1 /4
Shift a 16-bit register or memory
location left 1 bit.
SAL reg/mem16,CL D3 /4
Shift a 16-bit register or memory
location left the number of bits
specified in the CL register.
SAL reg/mem16,imm8 C1 /4 ib
Shift a 16-bit register or memory
location left the number of bits
specified by an 8-bit immediate
value.
SAL reg/mem32,1 D1 /4
Shift a 32-bit register or memory
location left 1 bit.
SAL reg/mem32,CL D3 /4
Shift a 32-bit register or memory
location left the number of bits
specified in the CL register.
SAL reg/mem32,imm8 C1 /4 ib
Shift a 32-bit register or memory
location left the number of bits
specified by an 8-bit immediate
value.
SAL reg/mem64,1 D1 /4
Shift a 64-bit register or memory
location left 1 bit.
SAL reg/mem64,CL D3 /4
Shift a 64-bit register or memory
location left the number of bits
specified in the CL register.
SAL reg/mem64,imm8 C1 /4 ib
Shift a 64-bit register or memory
location left the number of bits
specified by an 8-bit immediate
value.
SHL reg/mem8,1 D0 /4
Shift an 8-bit register or memory
location left 1 bit.
SHL reg/mem8,CL D2 /4
Shift an 8-bit register or memory
location left the number of bits
specified in the CL register.
SHL reg/mem8,imm8 C0 /4 ib
Shift an 8-bit register or memory
location left the number of bits
specified by an 8-bit immediate
value.
SHL reg/mem16,1 D1 /4
Shift a 16-bit register or memory
location left 1 bit.
SHL reg/mem16,CL D3 /4
Shift a 16-bit register or memory
location left the number of bits
specified in the CL register.