HP StorageWorks 1000 Modular Smart Array - Manual (Page 13)

MSA1000 Controller
13 MSA1000 Controller User Guide
Array Accelerator (Battery-backed Cache)
The Array Accelerator is a high-performance, upgradeable 256-MB SDRAM
DIMM read/write battery-backed cache that can increase performance in database
and fault-tolerant configurations. It performs both protected posted-write caching
and read-ahead caching, allowing data to be accessed much faster than from disk
storage.
In protected posted-write caching, data is written to the cache memory on the
Array Accelerator rather than directly to the drives. Later, when the MSA1000
storage system is idle, the controller writes the cached data to the drive array.
The read-ahead cache detects sequential accesses to the array, reads ahead data,
and stores the data in the cache until the next read access arrives. If the data is of a
sequential nature, the data can be loaded immediately into memory, avoiding the
latency of a disk access.
If the MSA1000 Controller fails before cached data is stored on the disk, the
Array Accelerator and its integrated batteries may be removed from one
MSA1000 Controller
and installed on a replacement controller. Any data in the
Array Accelerator that has not been written to the hard drive will be transferred to
the replacement MSA1000 Controller.
Array Accelerator Features
Other features of the Array Accelerator:
■ Mounted on a removable daughterboard (allows stored data to be moved to
another controller if the original controller fails)
■ Backed up with replaceable batteries
■ Upgradable to 512 MB (256 MB per controller)
■ Adjustable read/write ratio - usually set during array configuration but can be
changed at any time
■ 16-bit Error Checking and Correcting (ECC) SDRAM memory
ECC detects and corrects all single-bit memory errors. It also detects all
two-bit memory errors in any position, and most three- and four-bit memory
errors in a single SDRAM. With ECC, an entire memory chip can also fail
without data loss. This provides a high level of data integrity by ensuring the
correction of common memory errors without affecting performance.