IEI Integration AFL2-W15A-N270_W15A-L325 v1.01 - Manual (Page 102)

AFL2-W15A-N270/L325 Panel PC
Page 90
3.7.1 Northbridge Configuration
Use the Northbridge Chipset Configuration menu (BIOS Menu 25) to configure the
Northbridge chipset.
BIOS SETUP UTILITY
Main Advanced PCIPNP Boot Security Chipset Power Exit
Northbridge Configuration
⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
> ECC Configuration
⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
Memory CLK :333 MHz
CAS Latency (Tcl) :5.0
RAS/CAS Delay (Trcd) :5 CLK
Row Precharge Time (Trp) :5 CLK
Min Active RAS (Tras) :15 CLK
RAS/RAS Delay (Trrd) :3 CLK
Row Cycle (Trc) :20 CLK
Write Recover Time (Twr) :5 CLK
ÅÆ Select
Screen
↑ ↓ Select
Item
Enter Go to SubScreen
F1 General
Help
F10 Save and Exit
ESC Exit
v02.61 ©Copyright 1985-2006, American Megatrends, Inc.
BIOS Menu 23: Northbridge Chipset Configuration
3.7.2 ECC Configuration
Use the ECC Configuration menu (BIOS Menu 24) to set the ECC parameters.
BIOS SETUP UTILITY
Main Advanced PCIPNP Boot Security Chipset Power Exit
ECC Configuration
⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
ECC Mode
[Disabled]
DRAM ECC Enable [Disabled]
DRAM SCRUB REDIRECT [Disabled]
4-Bit ECC Mode [Disabled]
DRAM BG Scrub [Disabled]
Data Cache BG Scrub [Disabled]
L2 Cache BG Scrub [Disabled]
L3 Cache BG Scrub [Disabled]
ÅÆ Select
Screen
↑ ↓ Select
Item
Enter Go to SubScreen
F1 General
Help
F10 Save and Exit
ESC Exit
v02.61 ©Copyright 1985-2006, American Megatrends, Inc.
BIOS Menu 24: ECC Configuration Chipset Configuration