IEI Integration WAFER-945GSE v1.04 - Manual (Page 40)

WAFER-945GSE 3.5” Motherboard
Page 20
2.5.3 Intel
®
ICH7-M Low Pin Count (LPC) Interface
The ICH7-M LPC interface complies with the LPC 1.1 specifications. The LPC bus from
the ICH6 is connected to the following components:
BIOS chipset
Super I/O chipset
2.5.4 Intel
®
ICH7-M PCIe Bus
The Intel® ICH7-M southbridge chipset has four PCIe lanes. Two of the four PCIe lanes
are interfaced to PCIe GbE controller. A third PCIe lane is interfaced to a PCIe mini
socket.
2.5.4.1 PCIe GbE Ethernet
Two PCIe lanes are connected to two Realtek RTL8111C PCIe GbE controllers shown in
716H
Figure 2-11 below.