GE Industrial Solutions CAR2912TE series - Manual (Page 9)

GE
Preliminary Data Sheet
CAR2912TE series front-end
Input: 90Vac to 264Vac; Output: 12Vdc @ 2900W; 3.3 or 5Vdc @ 4A Standby
October 21, 2013 ©2013 General Electric Company. All rights reserved. Page 9
I ²C Bus Lock-Up detection: The device will abort any
transaction and drop off the bus if it detects the bus being
held low for more than 35ms.
Communications speed: Both 100kHz and 400kHz clock
rates are supported. The power supplies default to the
100kHz clock rate. The minimum clock speed specified by
SMBus is 10 kHz.
Packet Error Checking (PEC): The power supply will not
respond to commands without the trailing PEC because the
integrity of communications is compromised without packet
error correction deployment.
PEC is a CRC-8 error-checking byte, based on the polynomial
C(x) = x 8 + x 2 + x + 1, in compliance with PMBus™
requirements. The calculation is performed on all message
bytes, including the originating write address and command
bytes preceding read instructions. The PEC is appended to the
message by the device that supplied the last byte.
SMBAlert# : The power supply can issue SMBAlert# driven
from either its internal micro controller (µC) or from the I 2 C
bus master selector stage. That is, the SMBAlert# signal of the
internal µC funnels through the master selector stage that
buffers the SMBAlert# signal and splits the signal to the two
SMBAlert# signal pins exiting the power supply. In addition,
the master selector stage signals its own SMBAlert# request
to either of the two SMBAlert# signals when required.
The µC driven SMBAlert# signal informs the ‘master/host’
controller that either a STATE or ALARM change has occurred.
Normally this signal is HI. The signal will change to its LO level
if the power supply has changed states and the signal will be
latched LO until the power supply either receives a
‘clear_faults’ instruction as outlined below, or a read_status
(0xD0) or a status_word (0x79,) instructions are executed. If
the same alarm state is still present after the ‘clear_faults’
command has been received the status registers will revert
back into their alarm state but the SMBAlert# will not be
asserted. This response ensures that the ‘host’ controller
does not get bombarded by continuous SMBAlert# asserts for
the same fault. The ‘host’ will then be in a position to monitor
the power system for other events.
The signal will be triggered for any state change whether a
‘warning’ or a ‘fault’, including the following conditions;
• VIN under or over voltage
• Vout under or over voltage
• IOUT over current
• Over Temperature
• Fan Failure
• Communication error
• PEC error
• Invalid command
• Detected internal faults
The power supply will clear the SMBusAlert# signal (release
the signal to its HI state) upon the following events:
• Receiving a CLEAR_FAULTS command
• The main output recycled (turned OFF and then ON) via
the ON/OFF signal pin
• The main output recycled (turned OFF and then ON) by
the OPERATION command
• Bias power to the processor is recycled
Re-initialization: The I 2 C code is programmed to re-initialize if
no activity is detected on the bus for 5 seconds. Re-
initialization is designed to guarantee that the I 2 C µController
does not hang up the bus. Although this rate is longer than
the timing requirements specified in the SMBus specification,
it had to be extended in order to ensure that a re-initialization
would not occur under normal transmission rates. During the
few µseconds required to accomplish re-initialization the I 2 C
µController may not recognize a command sent to it. (i.e. a
start condition).
Read back delay: The power supply issues the SMBAlert #
notification as soon as the first state change occurred. During
an event a number of different states can be transitioned to
before the final event occurs. If a read back is implemented
rapidly by the host a successive SMBAlert# could be triggered
by the transitioning state of the power supply. In order to
avoid successive SMBAlert# s and read back and also to
avoid reading a transitioning state, it is prudent to wait more
than 2 seconds after the receipt of an SMBAlert# before
executing a read back. This delay will ensure that only the
final state of the power supply is captured.
Successive read backs: Successive read backs to the power
supply should not be attempted at intervals faster than every
one second. This time interval is sufficient for the internal
processors to update their data base so that successive
reads provide fresh data.
Global Broadcast: This is a powerful command because it
instruct all power supplies to respond simultaneously. A read
instruction should never be accessed globally. The power
supply should issue an ‘invalid command’ state if a ‘read’ is
attempted globally.
For example, changing the ‘system’ output voltage requires
the global broadcast so that all paralleled power supplies
change their output simultaneously. This command can also
turn OFF the ‘main’ output or turn ON the ‘main’ output of all
power supplies simultaneously. Unfortunately, this command
does have a side effect. Only a single power supply needs to
pull down the ninth acknowledge bit. To be certain that each
power supply responded to the global instruction, a READ
instruction should be executed to each power supply to verify
that the command properly executed. The GLOBAL
BROADCAST command should only be executed for write
instructions to slave devices.