B&B Electronics PCI-1711 - Manual - Manual (Page 11)

Chapter 1
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virtually no need to set any jumpers or DIP switches.
Flexible Input Types and Range Settings
The PCI-1710/1710L/1710HG/1710HGL/1711/1711L/1716/1716L features
an automatic channel/gain scanning circuit. This circuit design
controls multiplexer switching during sampling. Users can set different
gain values for each channel according to their needs for the corre-
sponding range of input voltage. The gain value settings thus selected
is stored in the SRAM. This flexible design enables multi-channel and
high-speed sampling for high-performance data acquisition.
On-board FIFO (First-In-First-Out) Memory
The PCI-1710/1710L/1710HG/1710HGL/1711/1711L/1716/1716L pro-
vides an on-board FIFO memory buffer, storing up 1 to 1K/4K A/D
samples. Users can either enable or disable the interrupt request
feature of the FIFO buffer. While the interrupt request for FIFO is
enabled, users are allowed to specify whether an interrupt request will
be sent with each sampling action or only when the FIFO buffer is half
saturated. This useful feature enables a continuous high-speed data
transfer with a more predictable performance on operating systems.
Optional D/A Output for Cost Savings
The PCI-1710/1710HG/1711/1716 goes further with 2 analog output
channels, while the PCI-1710L/1710HGL/1711L/1716L doesn’t. It is for
users to differentiate between the PCI-1710/1710HG/1711/1716 and the
PCI-1710L/1710HGL/1711L/1716L according to what they really need as
the best solution with no extra cost.
16 Digital Inputs and 16 Digital Outputs
The PCI-1710/1710L/1710HG/1710HGL/1711/1711L/1716/1716L pro-
vides 16 digital input channels and 16 digital output channels. Users
are left with great flexibility to design and customize their applications
according to their specific needs.
On-board Programmable Counter
The PCI-1710/1710L/1710HG/1710HGL/1711/1711L/1716/1716L is
equipped with a programmable counter, which can serve as a pacer
trigger for A/D conversions. The counter chip is an 82C54 or its
equivalent, which incorporates three 16-bit counters on a 10 MHz
clock. One of the three counters is used as an event counter for input