Rainbow Electronics ATAR862-8 - Manual (Page 69)

69
ATAR862-8
4589B–4BMCU–02/03
In RX mode, as soon as the SSI is activated (SIR = 0), 8 shift clocks are generated and
the incoming serial data is shifted into the shift register. This first telegram is automati-
cally transferred into the receive buffer and the SRDY set to 0 indicating that the receive
buffer contains valid data. At the same time an interrupt (if enabled) is generated. The
SSI then continues shifting in the following 8-bit telegram. If, during this time the first
telegram has been read by the controller, the second telegram will also be transferred in
the same way into the receive buffer and the SSI will continue clocking in the next tele-
gram. Should, however, the first telegram not have been read (SRDY = 1), then the SSI
will stop, temporarily holding the second telegram in the shift register until a certain point
of time when the controller is able to service the receive buffer. In this way no data is lost
or overwritten.
Deactivating the SSI (SIR = 1) in mid-telegram will immediately stop the shift clock and
latch the present contents of the shift register into the receive buffer. This can be used
for clocking in a data telegram of less than 8 bits in length. Care should be taken to read
out the final complete 8-bit data telegram of a multiple word message before deactivat-
ing the SSI (SIR = 1) and terminating the reception. After termination, the shift register
contents will overwrite the receive buffer.
Figure 67. Example of 8-bit Synchronous Transmit Operation
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
msb lsb
tx data 1 tx data 2 tx data 3
msb lsb msb lsb
Write STB
(tx data 2)
Write STB
(tx data 3)
Write STB
(tx data 1)
SC
SD
SIR
SRDY
Interrupt
(IFN = 0)
Interrupt
(IFN = 1)
ACT