Rainbow Electronics ATAR862-8 - Manual (Page 64)

64
ATAR862-8
4589B–4BMCU–02/03
Timer 3 Compare- and
Compare-mode Register Timer 3 has two separate compare registers T3CO1 and T3CO2 for the 8-bit stage of
Timer 3. The timer compares the content of the compare register with the current
counter value. If both match, it generates a signal. This signal can be used for the
counter reset, to generate a timer interrupt, for toggling the output flip-flop, as SSI clock
or as clock for the next counter stage. For each compare register, a compare-mode reg-
ister exists. These registers contain mask bits to enable or disable the generation of an
interrupt, a counter reset, or an output toggling with the occurrence of a compare match
of the corresponding compare register. The mask bits for activating the single-action
mode can also be located in the compare mode registers. When assigned to the com-
pare register a compare event will be suppressed.
Timer 3 Compare-Mode
Register 1 (T3CM1) Address: "B"hex - Subaddress: "2"hex
T3CM1 contains the mask bits for the match event of the Counter 3 compare register 1
T3CS1 T imer 3 C lock S ource select bit 1 T3CS1 TCS0 Counter 3 Input Signal (CL3)
T3CS0 T imer 3 C lock S ource select bit 0 1 1 System clock (SYSCL)
1 0 Output signal of Timer 2 (POUT)
0 1 Output signal of Timer 1 (T1OUT)
0 0 External input signal from T3I edge
detect
Bit 3 Bit 2 Bit 1 Bit 0
T3CM1 T3SM1 T3TM1 T3RM1 T3IM1 Reset value: 0000b
T3SM1 T imer 3 S ingle action M ask bit 1
T3SM1 = 0, disables single-action compare mode
T3SM1 = 1, enables single-compare mode. After this bit is set, the compare
register (T3CO1) is used until the next compare match.
T3TM1 T imer 3 compare T oggle action M ask bit 1
T3TM1 = 0, disables compare toggle
T3TM1 = 1, enables compare toggle. A match of Counter 3 with the compare
register (T3CO1) toggles the output flip-flop (TOG3).
T3RM1 T imer 3 R eset M ask bit 1
T3RM1 = 0, disables counter reset
T3RM1 = 1, enables counter reset. A match of Counter 3 with the compare
register (T3CO1) resets the Counter 3.
T3IM1 T imer 3 I nterrupt M ask bit 1
T3RM1 = 0, disables Timer 3 interrupt for T3CO1 register.
T3RM1 = 1, enables Timer 3 interrupt for T3CO1 register.