Rainbow Electronics ATtiny43U User Manual
Page 163
163
8048B–AVR–03/09
Figure 20-5. Parallel Programming Timing, Loading Sequence with Timing Requirements
Note:
1. t
WLRH
is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits commands.
2. t
WLRH_CE
is valid for the Chip Erase command.
Table 20-10. Parallel Programming Characteristics, V
CC
= 5V ± 10%
Symbol
Parameter
Min
Typ
Max
Units
V
PP
Programming Enable Voltage
11.5
12.5
V
I
PP
Programming Enable Current
250
μ
A
t
DVXH
Data and Control Valid before CLKI High
67
ns
t
XLXH
CLKI Low to CLKI High
200
ns
t
XHXL
CLKI Pulse Width High
150
ns
t
XLDX
Data and Control Hold after CLKI Low
67
ns
t
XLWL
CLKI Low to WR Low
0
ns
t
BVPH
BS1 Valid before PAGEL High
67
ns
t
PHPL
PAGEL Pulse Width High
150
ns
t
PLBX
BS1 Hold after PAGEL Low
67
ns
t
WLBX
BS2/1 Hold after WR Low
67
ns
t
PLWL
PAGEL Low to WR Low
67
ns
t
BVWL
BS1 Valid to WR Low
67
ns
t
WLWH
WR Pulse Width Low
150
ns
t
WLRL
WR Low to RDY/BSY Low
0
1
μ
s
t
WLRH
WR Low to RDY/BSY High
3.7
4.5
ms
t
WLRH_CE
WR Low to RDY/BSY High for Chip Erase
7.5
9
ms
t
XLOL
CLKI Low to OE Low
0
ns
t
BVDV
BS1 Valid to DATA valid
0
250
ns
t
OLDV
OE Low to DATA Valid
250
ns
t
OHDZ
OE High to DATA Tri-stated
250
ns
CLKI
XLXH
t
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
DATA
PAGEL/BS1
XA0
XA1/BS2
LOAD ADDRESS
(LOW BYTE)
LOAD DATA
(LOW BYTE)
LOAD DATA
(HIGH BYTE)
LOAD ADDRESS
(LOW BYTE)