Conversion. see, Figure 16-5 – Rainbow Electronics ATtiny43U User Manual
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Figure 16-5. ADC Timing Diagram, Single Conversion
When Auto Triggering is used, the prescaler is reset when the trigger event occurs, as shown in
below. This assures a fixed delay from the trigger event to the start of conversion. In
this mode, the sample-and-hold takes place two ADC clock cycles after the rising edge on the
trigger source signal. Three additional CPU clock cycles are used for synchronization logic.
Figure 16-6. ADC Timing Diagram, Auto Triggered Conversion
In Free Running mode, a new conversion will be started immediately after the conversion com-
pletes, while ADSC remains high. See
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Sign and MSB of Result
LSB of Result
ADC Clock
ADSC
ADIF
ADCH
ADCL
Cycle Number
1
2
One Conversion
Next Conversion
3
Sample & Hold
MUX and REFS
Update
Conversion
Complete
MUX and REFS
Update
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2
3
4
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10
11
12
13
Sign and MSB of Result
LSB of Result
ADC Clock
Trigger
Source
ADIF
ADCH
ADCL
Cycle Number
1
2
One Conversion
Next Conversion
Conversion
Complete
Prescaler
Reset
ADATE
Prescaler
Reset
Sample &
Hold
MUX and REFS
Update