Adv ance informa tion, See figure 43) – Texas Instruments TMS320C6202 User Manual
Page 65
TMS320C6202
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999
65
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MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0
†‡
(see Figure 43)
NO.
’C6202-200
’C6202-233
’C6202-250
UNIT
NO.
MASTER
SLAVE
UNIT
MIN
MAX
MIN
MAX
4
tsu(DRV-CKXH) Setup time, DR valid before CLKX high
12
2 – 3P
ns
5
th(CKXH-DRV)
Hold time, DR valid after CLKX high
4
5 + 6P
ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0
†‡
(see Figure 43)
NO.
PARAMETER
’C6202-200
’C6202-233
’C6202-250
UNIT
NO.
PARAMETER
MASTER§
SLAVE
UNIT
MIN
MAX
MIN
MAX
1
th(CKXL-FXL)
Hold time, FSX low after CLKX low¶
L – 2
L + 3
ns
2
td(FXL-CKXH)
Delay time, FSX low to CLKX high#
T – 2
T + 3
ns
3
td(CKXL-DXV)
Delay time, CLKX low to DX valid
–2
4
3P + 4
5P + 17
ns
6
tdis(CKXL-DXHZ)
Disable time, DX high impedance following last data bit from
CLKX low
–2
4
3P + 3
5P + 17
ns
7
td(FXL-DXV)
Delay time, FSX low to DX valid
H – 2
H + 4
2P + 2
4P + 17
ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§ S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T =
CLKX period = (1 + CLKGDV) * S
H =
CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L =
CLKX low pulse width
= (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
4
3
7
6
2
1
CLKX
FSX
DX
DR
5
Figure 43. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
ADV
ANCE INFORMA
TION