Adv ance informa tion, See figure 31 and figure 32) – Texas Instruments TMS320C6202 User Manual
Page 49
TMS320C6202
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999
49
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EXPANSION BUS SYNCHRONOUS HOST PORT TIMING
timing requirements with external device as bus master (see Figure 31 and Figure 32)
NO.
MIN
MAX
UNIT
1
tsu(XCSV-XCKIH)
Setup time, XCS valid before XCLKIN high
4
ns
2
th(XCKIH-XCS)
Hold time, XCS valid after XCLKIN high
2.3
ns
3
tsu(XAS-XCKIH)
Setup time, XAS valid before XCLKIN high
4
ns
4
th(XCKIH-XAS)
Hold time, XAS valid after XCLKIN high
2.3
ns
5
tsu(XCTL-XCKIH)
Setup time, XCNTL valid before XCLKIN high
4
ns
6
th(XCKIH-XCTL)
Hold time, XCNTL valid after XCLKIN high
2.3
ns
7
tsu(XWR-XCKIH)
Setup time, XW/R valid before XCLKIN high†
4
ns
8
th(XCKIH-XWR)
Hold time, XW/R valid after XCLKIN high†
2.3
ns
9
tsu(XBLTV-XCKIH)
Setup time, XBLAST valid before XCLKIN high‡
4
ns
10
th(XCKIH-XBLTV)
Hold time, XBLAST valid after XCLKIN high‡
2.3
ns
16
tsu(XBEV-XCKIH)
Setup time, XBE[3:0]/XA[5:2] valid before XCLKIN high§
4
ns
17
th(XCKIH-XBEV)
Hold time, XBE[3:0]/XA[5:2] valid after XCLKIN high§
2.3
ns
18
tsu(XD-XCKIH)
Setup time, XDx valid before XCLKIN high
4
ns
19
th(XCKIH-XD)
Hold time, XDx valid after XCLKIN high
2.3
ns
† XW/R input/output polarity selected at boot.
‡ XBLAST input polarity selected at boot.
§ XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.
switching characteristics with external device as bus master
¶
(see Figure 31 and Figure 32)
NO.
PARAMETER
MIN
MAX
UNIT
11
td(XCKIH-XDLZ)
Delay time, XCLKIN high to XDx low impedance
5
ns
12
td(XCKIH-XDV)
Delay time, XCLKIN high to XDx valid
15.5
ns
13
td(XCKIH-XDIV)
Delay time, XCLKIN high to XDx invalid
5
ns
14
td(XCKIH-XDHZ)
Delay time, XCLKIN high to XDx high impedance
18
ns
15
td(XCKIH-XRY)
Delay time, XCLKIN high to XRDY valid#
5
15.5
ns
20
td(XCKIH-XRYLZ)
Delay time, XCLKIN high to XRDY low impedance
5
15.5
ns
21
td(XCKIH-XRYHZ)
Delay time, XCLKIN high to XRDY high impedance#
2P + 5
3P + 15.5
ns
¶ P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
# XRDY operates as active-low ready input/output during host-port accesses.
ADV
ANCE INFORMA
TION