Texas Instruments TMS320C6202 - Manual (Page 35)

TMS320C6202
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999
35
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HOUSTON, TEXAS 77251–1443
SYNCHRONOUS-BURST MEMORY TIMING
timing requirements for synchronous-burst SRAM cycles (see Figure 15)
NO
’C6202-200 ’C6202-233 ’C6202-250
UNIT NO.
MIN MAX MIN MAX MIN MAX
UNIT
7 tsu(EDV-CKO2H)
Setup time, read EDx valid before CLKOUT2
high
2.5 2.1 2 ns
8 th(CKO2H-EDV) Hold time, read EDx valid after CLKOUT2 high 1.5 1.5 1.5 ns
switching characteristics for synchronous-burst SRAM cycles †‡ (see Figure 15 and Figure 16)
NO PARAMETER
’C6202-200 ’C6202-233 ’C6202-250
UNIT NO. PARAMETER
MIN MAX MIN MAX MIN MAX
UNIT
1 tosu(CEV-CKO2H)
Output setup time, CEx valid
before CLKOUT2 high
2P – 5.5 2P – 4.4 2P – 3.8 ns
2 toh(CKO2H-CEV)
Output hold time, CEx valid after
CLKOUT2 high
1 1 1 ns
3 tosu(BEV-CKO2H)
Output setup time, BEx valid
before CLKOUT2 high
2P – 5.5 2P – 4.4 2P – 3.8 ns
4 toh(CKO2H-BEIV)
Output hold time, BEx invalid
after CLKOUT2 high
1 1 1 ns
5 tosu(EAV-CKO2H)
Output setup time, EAx valid
before CLKOUT2 high
2P – 5.5 2P – 4.4 2P – 3.8 ns
6 toh(CKO2H-EAIV)
Output hold time, EAx invalid
after CLKOUT2 high
1 1 1 ns
9 tosu(ADSV-CKO2H)
Output setup time,
SDCAS/SSADS valid before
CLKOUT2 high
2P – 5.5 2P – 4.4 2P – 3.8 ns
10 toh(CKO2H-ADSV)
Output hold time,
SDCAS/SSADS valid after
CLKOUT2 high
1 1 1 ns
11 tosu(OEV-CKO2H)
Output setup time,
SDRAS/SSOE valid before
CLKOUT2 high
2P – 5.5 2P – 4.4 2P – 3.8 ns
12 toh(CKO2H-OEV)
Output hold time, SDRAS/SSOE
valid after CLKOUT2 high
1 1 1 ns
13 tosu(EDV-CKO2H)
Output setup time, EDx valid
before CLKOUT2 high§
2P – 5.5 2P – 4.4 2P – 3.8 ns
14 toh(CKO2H-EDIV)
Output hold time, EDx invalid
after CLKOUT2 high
1 1 1 ns
15 tosu(WEV-CKO2H)
Output setup time, SDWE/SSWE
valid before CLKOUT2 high
2P – 5.5 2P – 4.4 2P – 3.8 ns
16 toh(CKO2H-WEV)
Output hold time, SDWE/SSWE
valid after CLKOUT2 high
1 1 1 ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
‡ SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.
§ For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate
the ED enable time.
ADV
ANCE INFORMA
TION