Texas Instruments TMS320C6202 - Manual (Page 41)

TMS320C6202
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999
41
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77251–1443
HOLD/HOLDA TIMING
timing requirements for the HOLD/HOLDA cycles † (see Figure 23)
NO.
’C6202-200
’C6202-233
’C6202-250
UNIT
MIN MAX
3 toh(HOLDAL-HOLDL)Hold time, HOLD low after HOLDA low P ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
switching characteristics for the HOLD/HOLDA cycles
†‡
(see Figure 23)
NO. PARAMETER
’C6202-200
’C6202-233
’C6202-250
UNIT
MIN MAX
1 tR(HOLDL-EMHZ) Response time, HOLD low to EMIF Bus high impedance 4P § ns
2 td(EMHZ-HOLDAL) Delay time, EMIF Bus high impedance to HOLDA low 0 2P ns
4 tR(HOLDH-EMLZ) Response time, HOLD high to EMIF Bus low impedance 3P 7P ns
5 td(EMLZ-HOLDAH) Delay time, EMIF Bus low impedance to HOLDA high 0 2P ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
‡ EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10.
§ All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst case for this is an asynchronous read or write with
external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then the
minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
HOLD
HOLDA
EMIF Bus†
DSP Owns Bus
External Requestor
Owns Bus
DSP Owns Bus
C6202 C6202
1
3
2 5
4
† EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10.
Figure 23. HOLD/HOLDA Timing
ADV
ANCE INFORMA
TION