Texas Instruments TMS320C6202 - Manual (Page 3)

TMS320C6202
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999
3
POST OFFICE BOX 1443
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description
The TMS320C62x DSPs (including the TMS320C6202 device) are the fixed-point DSP family in the
TMS320C6000 platform. The TMS320C6202 (’C6202) device is based on the high-performance, advanced
VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI

), making this
DSP an excellent choice for multichannel and multifunction applications.
With performance of up to 2000 million instructions per second (MIPS) at a clock rate of 250 MHz, the ’C6202
offers cost-effective solutions to high-performance DSP programming challenges. The ’C6202 DSP possesses
the operational flexibility of high-speed controllers and the numerical capability of array processors. This
processor has 32 general-purpose registers of 32–bit word length and eight highly independent functional units.
The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and two 16-bit
multipliers for a 32-bit result. The ’C6202 can produce two multiply-accumulates (MACs) per cycle for a total
of 500 million MACs per second (MMACS). The ’C6202 DSP also has application-specific hardware logic,
on-chip memory, and additional on-chip peripherals.
The ’C6202 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals.
Program memory consists of two 128K-byte blocks, with one block configured as memory-mapped program
space, and the other block user-configured as cache or memory-mapped program space. Data memory
consists of two 64K-byte blocks of RAM. The peripheral set includes three multichannel buffered serial ports
(McBSPs), two general-purpose timers, an expansion bus (XB) that offers ease of interface to synchronous or
asynchronous industry-standard host bus protocols, and a glueless external memory interface (EMIF) capable
of interfacing to SDRAM or SBSRAM and asynchronous peripherals.
The ’C6202 has a complete set of development tools which includes: a new C compiler, an assembly optimizer
to simplify programming and scheduling, and a Windows

debugger interface for visibility into source code
execution.
device characteristics
Table 1 provides an overview of the ’C6202 DSP. The table shows significant features of each device, including
the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count.
Table 1. Characteristics of the ’C6202 Processors
CHARACTERISTICS DESCRIPTION
Device Number TMS320C6202
On-Chip Memory
2 Mbit Program Memory
(organized as 2 blocks)
1 Mbit Data Memory
(organized as 2 blocks)
Peripherals
3 Multichannel Buffered Serial Ports (McBSP)
2 General-Purpose Timers
External Memory Interface (EMIF)
Expansion Bus (XB)
Cycle Time 4 ns
Package Type
27 mm
×
27 mm, 352-Pin BGA (GJL)
18 mm × 18 mm, 384-Pin BGA (GLS)
Nominal Voltage
1.8 V Core
3.3 V I/O
ADV
ANCE INFORMA
TION
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