Texas Instruments TMS320C6202 - Manual (Page 51)

TMS320C6202
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999
51
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EXPANSION BUS SYNCHRONOUS HOST PORT TIMING (CONTINUED)
XBE1 XBE2 XBE3 XBE4
D1 D2 D3 D4
19
18
10
9
10
9
17
16
6
5
4
3
2
1
XCLKIN
XCS
XAS
XCNTL
XW/R†
XW/R†
XBLAST§
XBLAST§
XD[31:0]
8
7
8
7
XBE[3:0]/XA[5:2]‡
15
XRDY¶
15 20
21
† XW/R input/output polarity selected at boot
‡ XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.
§ XBLAST input polarity selected at boot
¶ XRDY operates as active-low ready input/output during host-port accesses.
Figure 32. External Host as Bus Master—Write
ADV
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TION