Texas Instruments TMS320C6202 - Manual (Page 46)

TMS320C6202
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999
46
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EXPANSION BUS SYNCHRONOUS FIFO TIMING (CONTINUED)
XA1 XA2 XA3 XA4
D1 D2 D3 D4
6
5
4 4
3 3
2 2
1 1
XFCLK
XCEx
XBE[3:0]/XA[5:2]†
XOE
XRE
XWE/XWAIT‡
XD[31:0]
† XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during synchronous FIFO accesses.
‡ XWE/XWAIT operates as the write enable signal XWE during synchronous FIFO accesses.
Figure 27. FIFO Read Timing
XA1 XA2 XA3 XA4
D1 D2 D3 D4
9
8
7 7
2 2
1 1
XFCLK
XCEx
XBE[3:0]/XA[5:2]†
XOE
XRE
XD[31:0]
XWE/XWAIT‡
† XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during synchronous FIFO accesses.
‡ XWE/XWAIT operates as the write enable signal XWE during synchronous FIFO accesses.
Figure 28. FIFO Write Timing
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