Texas Instruments TMS320C6202 - Manual (Page 50)

TMS320C6202
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999
50
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77251–1443
EXPANSION BUS SYNCHRONOUS HOST PORT TIMING (CONTINUED)
D1 D2 D3 D4
15
13
12
11
10
9
10
9
8
7
8
7
6
5
4
3
2
1
XCLKIN
XCS
XAS
XCNTL
XW/R†
XW/R†
XBE[3:0]/XA[5:2]‡
XBLAST§
XBLAST§
XD[31:0]
XRDY¶
15
14
20
21
† XW/R input/output polarity selected at boot
‡ XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.
§ XBLAST input polarity selected at boot
¶ XRDY operates as active-low ready input/output during host-port accesses.
Figure 31. External Host as Bus Master—Read
ADV
ANCE INFORMA
TION