Texas Instruments MSC1210 - Manual (Page 74)

Startup Timing
7-10
Figure 7−7. Serial Flash Programming Power-On Timing (EA is ignored)
Table 7−1. Signal Definitions for Reset Timing Diagrams
Symbol Parameter Min Max Unit
t
rw
RST Width 10 t
CLK
(1) — ns
t
rrd
RST rise to PSEN ALE internal pull high — 5 µ s
t
rfd
RST falling to PSEN and ALE start — (2 17 +512) t
CLK
(1) ns
t
rs
Input signal to RST falling setup time t
CLK
(1) — ns
t
rh
RST falling to input signal hold time (2 17 +512) t
CLK
(1) — ns
Notes: 1) tCLK is the Xtal clock period.