Texas Instruments MSC1210 - Manual (Page 179)

Watchdog Timer
14-5
Additional MSC1210 Hardware
Note:
The HCR0 and HCR1 registers may be set by the TI downloader application
at download time. It may also be set manually from within the source code
by including the following assembly language code:
CSEG AT 0807EH
DB 0FCH ; Value for HCR0
DB 0FFH ; Value for HCR1
When the MSC1210 is in programming/download mode, code address
807E
H
refers to the HCR0 register and 807F
H
refers to the HCR1 register.
This allows the values that are needed for HCR0/HCR1 to be hardcoded in
the source code rather than having to set the registers manually via the
downloader program.
14.3.2 Enabling Watchdog Timer
The watchdog timer is enabled by writing a 1 and then a 0 to the EWDT bit
(WDTCON.7). This may be accomplished, for example, with the following code:
WDTCON = 0x80; // Set EWDT
WDTCON = 0x00; // Clear EWDT – Watchdog enabled
The watchdog timer then begins a countdown that, unless reset by your pro-
gram, will trigger a watchdog reset or interrupt (depending on the configuration
of HCR0, described previously). The time after which the watchdog will be trig-
gered is also configured by the low five bits of the WDTCON SFR. These bits,
which may represent a value from 1 to 32 (0 to 31, plus 1), multiplied by the time
represented by HMSEC, defines the countdown time for the watchdog.
For example, if HMSEC is assigned a value that represents 100ms and
WDTCON is assigned a value of 7, the watchdog will automatically trigger after
800ms ([7 + 1]
S 100), unless the reset sequence is issued by the user program.
Therefore, a better approach to enabling the watchdog timer is:
WDTCON = 0x80; // Set EWDT
WDTCON = 0x07; // Clear EWDT, set timeout = 7, 800ms
Note:
There is an uncertainty of one count in the watchdog counter. That is to say,
the watchdog counter may occur a full HMSEC after the programmed time
interval. In the previous example, where the watchdog is set to trigger after
800ms, the watchdog may in fact trigger as late as 900ms.