Texas Instruments MSC1210 - Manual (Page 317)

Bit Addressable SFRs (alphabetical)
F-7
Bit-Addressable SFRs (alphabetical)
Program Status Word (PSW)
SFR Name: PSW
SFR Address: D0
H
Bit−Addressable: Yes
Bit−Definitions:
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Name CY AC F0 RS1 RS0 OV — P
Bit Address D7H D6H D5H D4H D3H D2H D1H D0H
CY—Carry Flag. Set or cleared by instructions ADD, ADDC, SUBB, MUL, and
DIV.
AC—Auxiliary Carry. Set or cleared by instructions ADD, ADDC.
F0—Flag 0. General flag available to developer for user-defined purposes.
RS1/RS0—Register Select Bits. These two bits, taken together, select the
register bank used when using R registers R0 through R7, according to the fol-
lowing table:
RS1 RS0 Register Bank Register Bank Addresses
0 0 0 00
H
−07
H
0 1 1 08
H
−0F
H
1 0 2 10
H
−17
H
1 1 3 18
H
−1F
H
OV—Overflow Flag. Set or cleared by instructions ADD, ADDC, SUBB, and
DIV.
P—Parity Flag. Set or cleared automatically by core to establish even parity
with the accumulator, so that the number of bits set in the accumulator plus the
value of the parity bit will always equal an even number.