Texas Instruments MSC1210 User Manual

Page 146

Offset DAC

12-10

12.8 Offset DAC

The input to the PGA can be shifted by half the full-scale input range of the PGA
by using the Offset DAC (ODAC) register (SFR address: 0xE6). The ODAC
register is an 8-bit value; the MSB is the sign and the seven LSBs provide the
magnitude of the offset. Using the ODAC does not reduce the noise perfor-
mance and increases the dynamic range of the ADC. The ODAC must be ap-
plied after any calibration is performed because the calibration will remove any
offset induced by the ODAC.

Offset

REF

PGA

Code

127

Note:

The input may only be shifted by half the full-scale input range. This means
that if the input voltage range is 5V, it can be shifted

2.5V. The range is divid-

ed by 256 and the LSB of the ODAC indicates an offset of that amount. Thus,
given an input voltage range of 5V and an ODAC of 10

(16), the input would

be shifted by 313mV (i.e., 5.000V / 256 = 19.53mV

16 = 312.5mV).

12.9 Modulator

The modulator is a single-loop second-order delta-sigma system. The modu-
lator clock speed is derived from the oscillator frequency divided by the ACLK
register (plus one) divided by 64. This can be summarized by the formula:

Analog Sample Rate

Oscillator Frequency

(ACLK

)

Thus, (given an oscillator frequency of 11.0592MHz), if ACLK = 8, the analog sig-
nal sample rate will be 11.0592MHz / (8 + 1) = 1.2288MHz / 64 = 19 200Hz.

The rate at which samples are made available to the user program running on
the MSC1210 is less than that of the analog sample rate. The data output rate
is determined by dividing the analog sample rate by the decimation value in
the ADCON2 (low byte, SFR address: 0xDE) and ADCON3 (high byte, SFR
address: 0xDF) registers. Therefore, in the above example that resulted in a
19 200Hz sample rate, if ADCON2 and ADCON3 together hold the value 1920,
your program would be provided sample data at a rate of 10Hz
(19 200Hz/1920 = 10Hz). The best noise performance is achieved with higher
decimation values.