Texas Instruments MSC1210 - Manual (Page 115)

Types of Interrupts
10-9
Interrupts
10.8 Types of Interrupts
Each interrupt can be categorized as one these types: serial, external, timer,
watchdog, or auxiliary.
10.8.1 Serial Interrupts
There are two interrupt flags that provoke a serial interrupt: receive interrupt (RI)
and transmit interrupt (TI). If either flag is set, a serial interrupt is triggered. As dis-
cussed in section 9.2, the RI bit is set when a byte is received by the serial port
and the TI bit is set when a byte has been sent.
This means that when the serial interrupt is executed, it may have been trig-
gered because the RI flag was set, the TI flag was set, or both flags were set.
Thus, your routine must check the status of these flags to determine what ac-
tion is appropriate. Additionally, because the MSC1210 does not automatically
clear the RI and TI flags, you must clear these bits in the interrupt handler.
A brief code example is in order:
INT_SERIAL:
JNB RI,CHECK_TI ;If RI flag is not set, we jump to check TI
MOV A,SBUF ;If we got here, the RI bit *was* set
CLR RI ;Clear the RI bit after we’ve processed it
CHECK_TI:
JNB TI,EXIT_INT ;If TI flag not set, we jump to exit point
CLR TI ;Clear TI bit before we send next character
MOV SBUF,#’A’ ;Send another character to the serial port
EXIT_INT:
RETI ;Exit interrupt handler
As shown, the code checks the status of both interrupts flags. If both flags were
set, both sections of code will be executed. Also note that each section of code
clears its corresponding interrupt flag. If the interrupt bits are not cleared, the
serial interrupt will be executed over and over until the bit is cleared. For this
reason, it is very important that the interrupt flags in a serial interrupt always
be cleared.
10.8.2 External Interrupts
The MSC1210 microcontroller has six external interrupt sources. These in-
clude the standard two interrupts of the 8052 architecture and four new
sources. The standard 8052 interrupts are INT0 and INT1. These are active
low, but can be configured to be edge- or level-triggered by modifying the value
of IT0 and IT1 (TCON, 88
H
). If ITx is assigned a logic 0, the interrupt is level-
triggered. The interrupt condition remains in force as long as the pin is low. If
ITx is assigned a logic 1, the interrupt is pseudo edge-triggered.
The pin driver of an edge-triggered interrupt must hold both the high, then the
low condition for at least one machine cycle (each) to ensure detection be-
cause the external interrupts are sampled. This means maximum sampling
frequency on any interrupt pin is 1/8th of the main oscillator frequency.