1 interrupt priority register 0 (ipr0), 1 reserved—bits 15–14, 4 reserved—bits 9–0 – Freescale Semiconductor 56F8122 User Manual
Page 57: 2 interrupt priority register 1 (ipr1), Figure 5-3 interrupt priority register 0 (ipr0), Figure 5-4 interrupt priority register 1 (ipr1)
Register Descriptions
56F8322 Technical Data, Rev. 10.0
Freescale Semiconductor
57
Preliminary
5.6.1
Interrupt Priority Register 0 (IPR0)
Figure 5-3 Interrupt Priority Register 0 (IPR0)
5.6.1.1
Reserved—Bits 15–14
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.1.2
EOnCE Breakpoint Unit 0 Interrupt Priority Level (BKPT_U0 IPL)—
Bits13–12
This field is used to set the interrupt priority levels for IRQs. This IRQ is limited to priorities 1 through 3.
It is disabled by default.
•
00 = IRQ disabled (default)
•
01 = IRQ is priority level 1
•
10 = IRQ is priority level 2
•
11 = IRQ is priority level 3
5.6.1.3
EOnCE Step Counter Interrupt Priority Level (STPCNT IPL)—
Bits 11–10
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.
It is disabled by default.
•
00 = IRQ disabled (default)
•
01 = IRQ is priority level 1
•
10 = IRQ is priority level 2
•
11 = IRQ is priority level 3
5.6.1.4
Reserved—Bits 9–0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.2
Interrupt Priority Register 1 (IPR1)
Figure 5-4 Interrupt Priority Register 1 (IPR1)
Base + $0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
0
BKPT_U0IPL
STPCNT IPL
0
0
0
0
0
0
0
0
0
0
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Base + $1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
0
0
0
0
0
0
0
0
0
RX_REG IPL
TX_REG IPL
TRBUF IPL
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0