Freescale Semiconductor 56F8122 - Manual (Page 39)

Peripheral Memory Mapped Registers
56F8322 Technical Data, Rev. 10.0
Freescale Semiconductor 39
Preliminary
Table 4-9 Quad Timer C Registers Address Map
(TMRC_BASE = $00 F0C0)
Register Acronym Address Offset Register Description
TMRC0_CMP1 $0 Compare Register 1
TMRC0_CMP2 $1 Compare Register 2
TMRC0_CAP $2 Capture Register
TMRC0_LOAD $3 Load Register
TMRC0_HOLD $4 Hold Register
TMRC0_CNTR $5 Counter Register
TMRC0_CTRL $6 Control Register
TMRC0_SCR $7 Status and Control Register
TMRC0_CMPLD1 $8 Comparator Load Register 1
TMRC0_CMPLD2 $9 Comparator Load Register 2
TMRC0_COMSCR $A Comparator Status and Control Register
Reserved
TMRC1_CMP1 $10 Compare Register 1
TMRC1_CMP2 $11 Compare Register 2
TMRC1_CAP $12 Capture Register
TMRC1_LOAD $13 Load Register
TMRC1_HOLD $14 Hold Register
TMRC1_CNTR $15 Counter Register
TMRC1_CTRL $16 Control Register
TMRC1_SCR $17 Status and Control Register
TMRC1_CMPLD1 $18 Comparator Load Register 1
TMRC1_CMPLD2 $19 Comparator Load Register 2
TMRC1_COMSCR $1A Comparator Status and Control Register
Reserved
TMRC2_CMP1 $20 Compare Register 1
TMRC2_CMP2 $21 Compare Register 2
TMRC2_CAP $22 Capture Register
TMRC2_LOAD $23 Load Register
TMRC2_HOLD $24 Hold Register
TMRC2_CNTR $25 Counter Register
TMRC2_CTRL $26 Control Register
TMRC2_SCR $27 Status and Control Register
TMRC2_CMPLD1 $28 Comparator Load Register 1
TMRC2_CMPLD2 $29 Comparator Load Register 2
TMRC2_COMSCR $2A Comparator Status and Control Register
Reserved
TMRC3_CMP1 $30 Compare Register 1