Freescale Semiconductor 56F8122 - Manual (Page 41)

Peripheral Memory Mapped Registers
56F8322 Technical Data, Rev. 10.0
Freescale Semiconductor 41
Preliminary
Table 4-11 Quadrature Decoder 0 Registers Address Map
(DEC0_BASE = $00 F180)
Quadrature Decoder is NOT available in the 56F8122 device
Register Acronym Address Offset Register Description
DEC0_DECCR $0 Decoder Control Register
DEC0_FIR $1 Filter Interval Register
DEC0_WTR $2 Watchdog Time-out Register
DEC0_POSD $3 Position Difference Counter Register
DEC0_POSDH $4 Position Difference Counter Hold Register
DEC0_REV $5 Revolution Counter Register
DEC0_REVH $6 Revolution Hold Register
DEC0_UPOS $7 Upper Position Counter Register
DEC0_LPOS $8 Lower Position Counter Register
DEC0_UPOSH $9 Upper Position Hold Register
DEC0_LPOSH $A Lower Position Hold Register
DEC0_UIR $B Upper Initialization Register
DEC0_LIR $C Lower Initialization Register
DEC0_IMR $D Input Monitor Register
Table 4-12 Interrupt Control Registers Address Map
(ITCN_BASE = $00 F1A0)
Register Acronym Address Offset Register Description
IPR0 $0 Interrupt Priority Register 0
IPR1 $1 Interrupt Priority Register 1
IPR2 $2 Interrupt Priority Register 2
IPR3 $3 Interrupt Priority Register 3
IPR4 $4 Interrupt Priority Register 4
IPR5 $5 Interrupt Priority Register 5
IPR6 $6 Interrupt Priority Register 6
IPR7 $7 Interrupt Priority Register 7
IPR8 $8 Interrupt Priority Register 8
IPR9 $9 Interrupt Priority Register 9
VBA $A Vector Base Address Register
FIM0 $B Fast Interrupt Match Register 0
FIVAL0 $C Fast Interrupt Vector Address Low 0 Register
FIVAH0 $D Fast Interrupt Vector Address High 0 Register
FIM1 $E Fast Interrupt Match Register 1
FIVAL1 $F Fast Interrupt Vector Address Low 1 Register
FIVAH1 $10 Fast Interrupt Vector Address High 1 Register