Freescale Semiconductor 56F8122 - Manual (Page 45)

Peripheral Memory Mapped Registers
56F8322 Technical Data, Rev. 10.0
Freescale Semiconductor 45
Preliminary
Table 4-20 Clock Generation Module Registers Address Map
(CLKGEN_BASE = $00 F2D0)
Register Acronym Address Offset Register Description
PLLCR $0 Control Register
PLLDB $1 Divide-By Register
PLLSR $2 Status Register
Reserved
SHUTDOWN $4 Shutdown Register
OSCTL $5 Oscillator Control Register
Table 4-21 GPIOA Registers Address Map
(GPIOA_BASE = $00 F2E0)
Register Acronym Address Offset Register Description Reset Value
GPIOA_PUR $0 Pull-up Enable Register 0 x 0FFF
GPIOA_DR $1 Data Register 0 x 0000
GPIOA_DDR $2 Data Direction Register 0 x 0000
GPIOA_PER $3 Peripheral Enable Register 0 x 0FFF
GPIOA_IAR $4 Interrupt Assert Register 0 x 0000
GPIOA_IENR $5 Interrupt Enable Register 0 x 0000
GPIOA_IPOLR $6 Interrupt Polarity Register 0 x 0000
GPIOA_IPR $7 Interrupt Pending Register 0 x 0000
GPIOA_IESR $8 Interrupt Edge-Sensitive Register 0 x 0000
GPIOA_PPMODE $9 Push-Pull Mode Register 0 x 0FFF
GPIOA_RAWDATA $A Raw Data Input Register —
Table 4-22 GPIOB Registers Address Map
(GPIOB_BASE = $00 F300)
Register Acronym Address Offset Register Description Reset Value
GPIOB_PUR $0 Pull-up Enable Register 0 x 00FF
GPIOB_DR $1 Data Register 0 x 0000
GPIOB_DDR $2 Data Direction Register 0 x 0000
GPIOB_PER $3 Peripheral Enable Register 0 x 00FF
GPIOB_IAR $4 Interrupt Assert Register 0 x 0000
GPIOB_IENR $5 Interrupt Enable Register 0 x 0000
GPIOB_IPOLR $6 Interrupt Polarity Register 0 x 0000
GPIOB_IPR $7 Interrupt Pending Register 0 x 0000
GPIOB_IESR $8 Interrupt Edge-Sensitive Register 0 x 0000
GPIOB_PPMODE $9 Push-Pull Mode Register 0 x 00FF
GPIOB_RAWDATA $A Raw Data Input Register —