Freescale Semiconductor 56F8122 - Manual (Page 46)

56F8322 Techncial Data, Rev. 10.0
46 Freescale Semiconductor
Preliminary
Table 4-23 GPIOC Registers Address Map
(GPIOC_BASE = $00F310)
Register Acronym Address Offset Register Description Reset Value
GPIOC_PUR $0 Pull-up Enable Register 0 x 007C
GPIOC_DR $1 Data Register 0 x 0000
GPIOC_DDR $2 Data Direction Register 0 x 0000
GPIOC_PER $3 Peripheral Enable Register 0 x 007F
GPIOC_IAR $4 Interrupt Assert Register 0 x 0000
GPIOC_IENR $5 Interrupt Enable Register 0 x 0000
GPIOC_IPOLR $6 Interrupt Polarity Register 0 x 0000
GPIOC_IPR $7 Interrupt Pending Register 0 x 0000
GPIOC_IESR $8 Interrupt Edge-Sensitive Register 0 x 0000
GPIOC_PPMODE $9 Push-Pull Mode Register 0 x 007F
GPIOC_RAWDATA $A Raw Data Input Register —
Table 4-24 System Integration Module Registers Address Map
(SIM_BASE = $00 F350)
Register Acronym Address Offset Register Description
SIM_CONTROL $0 Control Register
SIM_RSTSTS $1 Reset Status Register
SIM_SCR0 $2 Software Control Register 0
SIM_SCR1 $3 Software Control Register 1
SIM_SCR2 $4 Software Control Register 2
SIM_SCR3 $5 Software Control Register 3
SIM_MSH_ID $6 Most Significant Half JTAG ID
SIM_LSH_ID $7 Least Significant Half JTAG ID
SIM_PUDR $8 Pull-up Disable Register
Reserved
SIM_CLKOSR $A Clock Out Select Register
SIM_GPS $B GPIO Peripheral Select Register
SIM_PCE $C Peripheral Clock Enable Register
SIM_ISALH $D I/O Short Address Location High Register
SIM_ISALL $E I/O Short Address Location Low Register
Table 4-25 Power Supervisor Registers Address Map
(LVI_BASE = $00 F360)
Register Acronym Address Offset Register Description
LVI_CONTROL $0 Control Register
LVI_STATUS $1 Status Register