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4 most significant half of jtag id (sim_msh_id), 5 least significant half of jtag id (sim_lsh_id), 6 sim pull-up disable register (sim_pudr) – Freescale Semiconductor 56F8122 User Manual

Page 83: 1 reserved—bits 15–12, 2 reset—bit 11

4 most significant half of jtag id (sim_msh_id), 5 least significant half of jtag id (sim_lsh_id), 6 sim pull-up disable register (sim_pudr) | 1 reserved—bits 15–12, 2 reset—bit 11 | Freescale Semiconductor 56F8122 User Manual | Page 83 / 137 4 most significant half of jtag id (sim_msh_id), 5 least significant half of jtag id (sim_lsh_id), 6 sim pull-up disable register (sim_pudr) | 1 reserved—bits 15–12, 2 reset—bit 11 | Freescale Semiconductor 56F8122 User Manual | Page 83 / 137
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