2 once enable (once ebl)—bit 5, 3 software reset (sw rst)—bit 4, 4 stop disable (stop_disable)—bits 3–2 – Freescale Semiconductor 56F8122 User Manual
Page 81: 5 wait disable (wait_disable)—bits 1–0, 2 sim reset status register (sim_rststs), 1 reserved—bits 15–6, 2 software reset (swr)—bit 5
2 once enable (once ebl)—bit 5, 3 software reset (sw rst)—bit 4, 4 stop disable (stop_disable)—bits 3–2 | 5 wait disable (wait_disable)—bits 1–0, 2 sim reset status register (sim_rststs), 1 reserved—bits 15–6, 2 software reset (swr)—bit 5 | Freescale Semiconductor 56F8122 User Manual | Page 81 / 137 This manual is related to the following products: