Altera DDR Timing Wizard - Manual (Page 91)

Altera Corporation 3–31
November 2007 DDR Timing Wizard User Guide
Using the dtw_timing_analysis.tcl Script
To avoid assigning these resynchronization registers’ locations manually,
you can use a tcl script called relative_constraint.tcl. This script is
available with the Legacy_PHY.qpf example design that is downloadable
with
AN328: Interfacing DDR2 SDRAM in Stratix II, Stratix II GX, and Arria
GX Devices , and is also included in Quartus II 7.2 SP1 and later releases in
the Quartus II installation direcory (common/tcl/apps/relcon).
f
For more information on the script, please refer to Appendix E of AN328:
Interfacing DDR2 SDRAM in Stratix II, Stratix II GX, and Arria GX Devices .
The example design in AN328: Interfacing DDR2 SDRAM in Stratix II,
Stratix II GX, and Arria GX Devices uses two batch files, called resynch.bat
and core_registers.bat. The resynch.bat file aligns the resynchronization
registers to the same column as the pin feeding them, as the DQ pin
locations were changed from the default assignments due to the board
pin-outs. The core_registers.bat places the second resynchronization
registers and the intermediate resynchronization registers closer to the
pins to meet core timing.
Both batch files use –pin_range and –reg_range argument since one
pin is actually related to two registers (due to the double-data rate
transfer). An example of the code in the resynch.bat file is shown below
where each DQ group (in this care ddr2_dq[7:0]) is called twice to be
associated with the resynchronization registers with index [7:0] and
with index [15:8]:
quartus_sh -t relative_constraint.tcl -project
Legacy_PHY -pin_name *ddr2_dq[* -reg_name
"*0:*|resynched_data[*]" -show_regs -reg_range 7:0
-pin_range 7:0 -row_offset 1 -apply
quartus_sh -t relative_constraint.tcl -project
Legacy_PHY -pin_name *ddr2_dq[* -reg_name
"*0:*|resynched_data[*]" -show_regs -reg_range 15:8
-pin_range 7:0 -row_offset 1 -apply
Note that you need to distinguish the resynchronization registers by
group, hence the use of "0" in the wildcard, or else the
relative_constraint.tcl
script grabs all the registers with
"resynched_data" as part of the name (which equals to 144 registers in
this example).
If you have multiple memory controllers in the design, you also need to
distinguish the name of each controller so that the registers get the correct
placement by the script.