Altera DDR Timing Wizard - Manual (Page 47)

Altera Corporation 2–35
November 2007 DDR Timing Wizard User Guide
Getting Started
DTW requires the following numbers to be entered:
● Nominal memory to FPGA trace (DQ and DQS traces)
The midpoint between the maximum DQ/DQS trace delay and
the minimum DQ/DQS trace delay, using typical delays. For
example:
nominal_tpd (memory_to_FPGA) = (max(DQ, DQS) + min (DQ,
DQS)) / 2.
● Nominal FPGA output to memory trace
The midpoint between the maximum CK/CK# trace delay and
the minimum CK/CK# trace delay, using typical delays. For
example:
nominal_tpd (FPGA_to_memory) = (max(CK, CK#) + min (CK,
CK#)) / 2.
● Nominal feedback clock trace
The average delay of the two differential feedback clock traces.
For example:
nominal_tpd (feedback_trace) = (feedback_clock_p +
feedback_clock_n) / 2
For a single-ended feedback clock, just use the delay of that
clock trace.
● Board tolerance (measurement error in the above delays)
Maximum ± percent variation of the trace delays due to board
manufacturing tolerances and environmental conditions. Note
the other board delays specified use typical delays that do not
include these variations.
● Skew between wires in a data group (maximum delay difference
between DQS and DQ/DM board traces)
Maximum difference of DQ and DM board traces relative to
DQS/DQS# board traces.