Altera DDR Timing Wizard - Manual (Page 89)

Altera Corporation 3–29
November 2007 DDR Timing Wizard User Guide
Using the dtw_timing_analysis.tcl Script
Figure 3–15. Preparing for Dedicated Address/Command Clock
1
Checking the Insert extra pipeline registers in the datapath
option propagates the address and command clock to the
top-level design, which makes it easier to connect a different
PLL output (other than the default negative edge of the system
clock) if the timing results after compilation show that you need
to shift this clock. However, there will be an additional clock
cycle of latency since a second pipeline register is inserted
between the memory controller and the address and command
outputs. This means that you cannot use this option if you use a
registered DIMM, as address and command signals are
registered on-board in registered DIMMs. Only use this option
if the Insert pipeline registers on address and command
outputs
option is also checked.