Altera DDR Timing Wizard User Manual
Page 51
Altera Corporation
2–39
November 2007
DDR Timing Wizard User Guide
Getting Started
while in HardCopy II, these numbers need to be calculated
separately based on the design. HardCopy II designs must use this
explicit clock uncertainties option. When the option is not checked,
as in
, you specify the clock skew adder,
PLL jitter, compensation error, and phase shift error individually.
DTW automatically populates these fields based on the synthesized
design. When the option is checked, the individual numbers are
added up to create clock uncertainty requirements for data capture,
fedback-clock resynchronization, write data, address, and t
DQSS
specifications.
When the Use explicit clock uncertainties option is checked, you
must import clock uncertainties from the HardCopy II Clock
Uncertainty Calculator. The calculator is available by request when
you have a design with memory interfaces targeting HardCopy II
devices. You should have used this calculator before the design
review process. Contact your Field Applications Engineers (FAEs)
for access to the calculator.
f
The duty cycle distortion, PLL uncertainties, DQS
uncertainties, and skew parameters are specified in the
.
also display estimated t
CO
numbers for the clocks. These
are only used when using Classic Timing Analyzer as DTW uses t
CO
skew to determine the write timing constraints. The numbers shown
in
CO
estimates that the DTW uses to
generate the timing constraints before the design in compiled. After
you compile the design, rerun the DTW and click the Extract tcos
button to use actual timing data for more accurate timing constraints.
(Note that this process may take some time if your design is large.)
You can also use the -extract_tcos yes option when running
dtw_timing_analysis.tcl
. Click on the Defaults for
to reset any of the numbers with the pre-compiled numbers.
1
Extract tcos
assumes that you are using DDIOs for your
memory clocks. If you are targeting HardCopy II, you need
to use dedicated PLL clock outputs for your memory clocks.
In this case, you have to manually enter the CK/CK# t
CO
s
for both timing models.
The bottom of
shows the option to either use Both fast
and slow timing model tcos
or to use Slow timing model tcos and
Fast timing model tcos
separately. You can use either mode, but
Altera recommends using the separate timing model for memory
interface designs running at or above 200 MHz.