Altera DDR Timing Wizard - Manual (Page 67)

Altera Corporation 3–7
November 2007 DDR Timing Wizard User Guide
Using the dtw_timing_analysis.tcl Script
Figure 3–2. Script Results as Part of Timing Analyzer Results
Each .dwz file folder under Memory Interface Timing has three panels:
■ Timing Summary
Figure 3–3 shows an example of the Timing Summary panel.
Figure 3–3. Example Design Timing Summary
This panel shows current and ideal margins for each timing path for
the interface. Current margin is the smallest margin of the path
calculated from the setup and hold timing margins for both fast and
slow timing models (also shown in this panel). The current margin
shows how much delay you can shift either to the right or left of the
current shift before timing breaks the design requirements.
1
When the design uses slow timing model tcos only, the
script automatically runs fast timing model timing analysis
to get the fast timing model timing margin.
Table 3–2 shows the paths that are analyzed for the different
memory interface implementations.